1. Field of the Invention
The present invention relates to the technical field of dynamic random access memory (DRAM) and, more particularly, to a memory test system with advance features for completed memory system.
2. Description of Related Art
For the past years, with the advance of semiconductor processes, the capacity of cells in a synchronous dynamic random access memory
(SDRAM) can be as high as 4 Giga bytes or more. The amount of data transfer at each data pad can reach up to 1600 bps/pin or more. In a SDRAM system, the SDRAM has rapidly increased in density and speed, and the transmission speed required for the electrical signal on the traces of the PCB connecting the pins of the integrated circuit (IC) is also increased rapidly. Accordingly, the SDRAM becomes an essential storage for either personal computer systems or consumer electronic products, and plays the role of a main memory.
Since SDRAM has very high density and fast operating speed, a SDRAM access system is required for accessing and handling the SDRAM. The SDRAM access system generally includes a memory controller, a high speed pad, a high speed package, a PCB, and at least one SDRAM.
The memory controller and the high speed pad are disposed in an IC. The high speed package is a communication interface between the IC and the PCB. The traces on the PCB connect the pins of the IC and the SDRAM. The memory controller includes digital and analog circuits. The digital circuit converts signals of a system bus into the SDRAM signals. The analog circuit processes the analog signals, and handles the external data and commands that are inputted to or outputted from the IC.
The high speed package solves the problem of high speed signals communicating from the IC to the external SDRAM. By means of the traces on the PCB, the SDRAM is used as a storage device at the terminal of the access system. As cited, a completed memory access system has multiple signal paths, and is a complicated and multi-field system.
In addition to the complicated system design, the signal integrity and the power integrity in designing a high speed memory access system have the dominant impact on system stability and smooth operation. Due to the advanced SDRAM standards, designing a higher performance and quality memory system is required for operating at higher speed and lower working voltage at the signal integrity and the power integrity.
Since the memory access system has multiple signal paths, verifying the memory access system becomes more and more difficult in the advanced SDRAM standards. For a computer or embedded system, the verification and test method for a memory access system becomes more and more difficult and important.
In the technical field of memory tests, various memory test methods are proposed. A build-in-self-test (BIST) is widely used, which implements a BIST circuit in the SDRAM to test the cells, controller, and peripheral circuits inside the SDRAM. U.S. Pat. Nos. 6,154,860, 6,182,257, 6,253,340, 6,230,290, and 6,415,403 are related to the BIST issues. However, the BIST circuit can test only the internal circuits of the SDRAM, not for the entire SDRAM system containing the memory controller, high speed pad, high speed package, PCB, and SDRAM. Namely, the BIST circuit cannot test the entire SDRAM system.
U.S. Pat. No. 6,131,149 granted to Lu, et al. for an “Apparatus and method for reading data from synchronous memory with skewed clock pulses” has disclosed a test method related to a static random access memory (SRAM). However, the complexity of a SRAM is much lower than that of a
SDRAM. U.S. Pat. No. 6,047,393 granted to Yamada for “Memory testing apparatus” has disclosed a test method related to a direct current (DC) for a memory, which cannot meet with the requirement of a modern SDRAM access system.
In the known patents, such as U.S. Pat. No. 6,715,096 granted to Kuge for “Interface circuit device for performing data sampling at optimum strobe timing by using stored data window information to determine the strobe timing”, U.S. Pat. No. 6,940,768 granted to Dahlberg, et al. for “Programmable data strobe offset with DLL for double data rate (DDR) RAM memory”, and U.S. Pat. No. 7,355,387 granted to LaBerge for “System and method for testing integrated circuit timing margins”, there is disclosed a test method related to the timing residual of a SDRAM interface, which does not introduce different operating means and conditions, and the result is obtained at the optimal conditions only, not at the poorer conditions.
U.S. Pat. No. 4,835,744 granted to Todd, et al. for a “Marine seismic data acquisition system and method” has disclosed a completed test system with comparative data memory which uses a data memory to handle the test data to be compared. However, such a way increases the system cost.
U.S. Pat. No. 4,481,627 granted to Beauchesne, et al. for an “Embedded memory testing method and apparatus” has disclosed a testing method for an embedded memory, which can be used only in an embedded memory because there are no high speed pad and circuit board.
U.S. Pat. No. 5,657,443 granted to Krech, Jr. for an “Enhanced test system for an application-specific memory scheme” has disclosed a test system for testing all cells of a SDRAM, which cannot test the entire SDRAM system because, in addition to the SDRAM, a memory controller, a high speed pad, a high speed package, and a PCB are included in the SDRAM system.
U.S. Pat. No. 5,912,852 granted to Lawrence, et al. for a “Synchronous memory test method” has disclosed a SDRAM test method to find a SDRAM digital protocol.
U.S. Pat. No. 5,682,472 granted to Brehm, et al. for a “Method and system for testing memory programming devices” and U.S. Pat. No. 7,315,969 granted to Jakobs for a “Memory module with a test device” have disclosed a multi-SDRAM test method focusing on how to effectively test multiple SDRAMs.
In U.S. Pat. No. 5,155,844 granted to Cheng, et al. for a “Background memory test during system start up”, a test is performed before the SDRAM is normally accessed to thereby verify the cells of the SDRAM. Such a way cannot test the SDRAM at a normal access, and especially at high loading.
Therefore, it is desirable to provide an improved memory test system to mitigate and/or obviate the aforementioned problems.